What is a 3-state bus buffer

Tristate logic, basis and practice

 


introduction

The heading digital technology contains under Basic logical links the basics of the AND, NAND, OR, NOR, EXOR and EXNOR circuits, but the basis of the tristate logic is missing. Strictly speaking, it is not a logic circuit in the usual sense. Nevertheless, the tristate logic is an integral and very important part of the TTL and CMOS logic circuit families. This electronics mini-course describes what the tristate logic is and what it is used for, which in this special case expands the logic connections in the category of digital technology. It is also a basic course, but incorporates experiment and practice in the smooth transition.



What is tristate logic?

It does that as the name suggests: The tristate logic generates three logical states at the output of a gate. This tristate logic is available as quad buffers of the type 74LS125 and 74LS126 in TTL and 74HC125 and 74HC126 in HCMOS. However, we are only concerned here with the high-speed CMOS family 74HCxxx. There are also tristate logic circuits at the outputs of more complex digital ICs, such as the Tristate Octal D-Type Latch 74HC533 or the Tristate Octal D-Type Flip-flop 74HC534. Using the example of the quad buffers mentioned above, we want to get to know the tristate logic. We look at Figure 1:

The tri-state quad buffer 74HC125 is shown on the left side of the picture and 74HC126 on the right side of the picture. The only difference between these two IC types is that the 74HC125 works with an active LOW level and the 74HC126 with an active HIGH level. For more precise information, consult the data sheets.

Please note the two truth tables arranged below the circuit diagrams. A is the signal input and Y is the signal output. C is the control input. If this is set to LOW in one of the buffers of the 74HC125, then output Y follows the logic state of input A. With the 74HC126, this applies if the control input is logic HIGH.

If the control input is set to HIGH on the 74HC125 or LOW on the 74HC126, output Y is in state Z. This means that it is high-resistance. Regardless of the logical input level A, output Y remains high-impedance. There is neither a connection to Vcc nor to GND. Y is simply not connected anywhere inside the IC in Z mode.

The purpose of this third logic state is that such tristate outputs can be connected in parallel, provided, however, that only one tristate output is activated at a time. If two tristate outputs are activated, with one output being HIGH and the other being LOW, there is a short circuit! You should therefore make sure that, especially when switching slowly (mechanical switch), the tristate buffer that is still active is switched off before the other one switches on. This is called breaking-before-making. You get to know this term if you deal with data sheets for integrated analog switches (analog switches) which can switch analog signals. These components are also called analog multiplexers.



How does the tristate logic work?

Figure 2 shows how one can experimentally realize a tristate buffer with a quad dual input NAND gate, e.g. of the type 74HC00, and two normally-off FETs, one N and P channel type. Functionally, this corresponds to a buffer of the 74HC126 that is active when control input C is set to HIGH. In reality, the tristate function is more easily integrated in an IC. A few MOSFETs are sufficient for the entire tristate buffer. So it's just about visualization and an experiment, if someone wants to do it. Instead of N- and P-channel MOSFETs, any bipolar NPN (e.g. BC109) and PNP transistors (e.g. BC178) can be used. It is important that resistors are connected between the IC outputs and the bases in order to limit the base currents to reasonable values. See Figure 2 on the right.

Such an experiment is well suited for electronics class. With modular systems, something like this can be built up in blocks and if it has blocks with LED displays, it can be designed very clearly. For my part, this is just an idea, please do not ask me any details, because I am not familiar with modular systems.


How does the tristate experiment work?

IC: A1 to IC: A4 are the four NAND gates of a 74HC00. T1 is a P-channel MOSFET, e.g. the logic level MOSFET BS110 and T2 is an N-channel MOSFET, e.g. the logic level MOSFET BS100. The NAND gates IC: A1 and IC: A4 work as inverters. Your two inputs are connected in parallel. However, you can just as easily set one of the inputs to HIGH by connecting it to the positive operating voltage. Regarding open inputs of logic circuits you can read more in:


The logic signals are entered at the two inputs A and C, at the output Y and on the lines interrupted by dashes. The sequence LOW, HIGH and HIGH can be seen at control input C, represented by L | H | H. At signal input A it is X | L | H. X of A corresponds to L of C and in the following step L of A corresponds to H of C. Likewise, Z of Y corresponds to L of C and X of A. X means that it does not matter whether LOW or HIGH is present. Z means that both MOSFETs T1 and T2 are open and output Y is high-resistance. This type of representation method of logic levels is hardly found in an "official" circuit. As a rule, tables, so-called truth tables, are created for the representation of logical signals. This is also correct, because the representation is clearer for many logic values. However, if you only want to display a few logic values, the method of displaying them directly in the circuit diagram is sometimes clearer. It is easier to associate the logic levels with the circuit. At least that's how I often design a simple logic circuit with paper and pencil. A simple and intuitive method that I am always happy to recommend.

When C = LOW, this logic level dominates the two NAND gates IC: A2 and IC: A3. Their outputs are HIGH, regardless of which logic level is present at their second inputs. The gate of the P-channel MOSFET T1 receives a HIGH level. Its drain-source path is open. T1 locks. IC: A4 inverts the logic level at the output of IC: A3. The gate of the N-channel MOSFET T2 receives a LOW level. Its drain-source path is open. T2 also blocks. This is the logic state Z at output Y. This state is enforced solely by the LOW level at control input C. In this state, output Y may be connected to another output that has a LOW or HIGH level. We will see this in more detail later using examples.

If C = HIGH, IC: A2 and IC: A3 are enabled to accept the logic level at input A and invert it by IC: A1. If A = LOW, an input of IC: A2 is LOW and its output is consequently HIGH. T1 is open. IC: A1 inverts input A. Both inputs of IC: A3 are on HIGH and its output on LOW. IC: A4 inverts this logic level to HIGH. HIGH at the gate of T2 turns it on. Output Y is thus connected to GND. Y has a LOW level corresponding to input A, as it should be with a non-inverting buffer.

If A = HIGH, both inputs of IC: A2 are set to HIGH. Its output is LOW. The gate of T1 is also on LOW. T1 conducts. HIGH from input A is inverted to LOW by IC: A1. This generates a HIGH level at the output of IC: A3 and a LOW level at the gate of T2. T2 is open. Output Y is thus HIGH and this corresponds to the logic level at input A.



Tristate makes switching easy

Figure 3 shows on the left side of the picture how to switch between two logic signals with conventional logic modules. NAND gates are used here. A NAND gate can also be used as an inverter (IC: A) by connecting both inputs in parallel or connecting the input that is not required to the positive operating voltage. In this case a 74HC00 is required entirely. If the control input C is set to LOW - the switch is open - the output of IC: B2 is set to HIGH, regardless of the logic level at input B. In this case, inverter IC: A sets one input of IC: B1 to HIGH. This means that IC: B1 transmits and inverts the input signal from A. The input of IC: B3, which is connected to the output of IC: B2, is constantly HIGH. IC: B3 is therefore open to the signal from IC: B1 and inverts it to output Y. This double inversion of IC: B1 and IC: B3 generates the logical signal identical to A at Y. If C is set to HIGH - switch is closed - the same explanation applies, only with the difference that in the function IC: B1 and IC: B2 are swapped. Y is now identical to B.

Let's come back to the main topic of tristate logic. In the middle part of the picture we can see how the circuit with tristate logic can be implemented more easily by simply connecting the tristate outputs in parallel. If C = LOW, IC: B1 is active and output Y follows input A. If C = HIGH, IC: B2 is active and output Y follows input B.

You can save the inverter in both circuit diagrams by using a toggle switch. How it is done is shown in the small diagram on the right-hand side of the picture. You need both control connections and a second pull-down resistor. In this way, the breaking-before-making described above has also been fulfilled. In the case of the inverter solution, this is not the case, but the moment of switching, in which both outputs are active, is extremely short. Nonetheless, for this very reason, it is advisable to block directly at the IC supply using a ceramic or multilayer capacitor with a value of around 100 nF. This inoperative capacitor takes over the power supply of the IC during such a transient process. At this very short instant, in the time range of around 10 ns, a slightly higher current occurs. This must be provided by this blocking capacitor.

A little homework for the interested reader: If you use the 74HC126 (see Fig. 1) instead of the 74HC125, you can convert a tri-state buffer that has remained free as an inverter. All you need is an additional pull-up resistor. Signal input A is permanently switched to LOW and the logic level of control input C is inverted at signal output Y. Where does the pull-up resistor belong now? What does this simple circuit look like?



Tristate makes switching even easier

Figure 4 shows that it is even easier with a three-stage switch with tristate logic. The circuit on the left side of the picture requires a NAND gate with three inputs and three NAND gates with two inputs each. That's two ICs. From this one can conclude that the NAND gate at the output must have as many inputs as the circuit has inputs. The tristate solution on the right-hand side of the picture shows how easily and elegantly the tristate outputs can be connected in parallel.

The decade divider, which downshifts a clock frequency in 1:10 steps, shows an elegant tristate switching logic using a seven-stage rotary switch in Chapter 4 and Figure 6 in:

Here is a switching scheme reduced to tristate switching in Figure 5:



No complex bus circuits without tristate ...

Get the data sheet for the Octal Tristate Transceiver 74HC245 and look closely at the circuit. With the knowledge of tristate logic that we have acquired so far, we can understand how this circuit works.

There are two tristate control inputs, / OE (Output Enable) and DIR (Direction). Instead of / OE there is also the designation / G. These two control inputs control all eight integrated buffers for the byte data flow in one or all eight integrated buffers opposite for the byte data flow in the opposite direction. The responsibility for controlling the direction of the byte flow rests with DIR. If DIR = LOW, the data flow follows from B to A, if DIR = HIGH, the data flow follows from A to B. This is only possible because one buffer row is inactive, i.e. the outputs are switched to Z mode, while the other buffer row is active and transfers the byte-wise input signal to the byte-wise output. But that is not all. The control input / G allows all outputs, regardless of which connections are switched to the active output by DIR, to be set to Z mode (/ G = HIGH). This in turn allows these outputs to be connected in parallel with other tri-state outputs external to the IC.

Conclusion at the end: Without the invention of the tristate logic, modern computer technology with its complex bus systems would hardly have ever been possible. A small, fundamental invention with a huge impact ...



Thomas Schaerer, July 29, 2001; 12/02/2002; 03/15/2003 (dasELKO); 12/18/2003; 10/20/2005; 02/20/2006